The present inventions relate generally to data processing systems, and more specifically, to data processing systems having a capability to identify executional delays (such as stall conditions), and record information regarding those delays.
Data processing systems, such as systems with superscalar and pipelined processors, may experience “stall conditions” or “stalls,” which are events that delay the completion of one or more instructions by a clock cycle or more. Stalls may generally be classified into “front-end stalls” and “back-end stalls.” Front-end stalls may include stalls that cause the pipeline to be empty such that instructions cannot be dispatched into the pipeline. Examples of front-end stalls include I-cache misses, branch mispredicts, instruction effective-to-real address translation (ERAT) misses, Simultaneous Multi-Threading (SMT) effects, etc. Back-end stalls may include stalls that involve instructions in the pipeline but the oldest group of instructions is not completing. Examples of back-end stalls include data cache misses, rejects, flushes, and long latency operations, such as fixed-point divide, etc.